Overview
Semiconductor industry is hitting the utilization wall, resulting in parallel and heterogeneous many-core architectures. Applications have to exploit the available parallelism and heterogeneity to meet their functional and non-functional requirements and to gain performance improvements.
A main challenge originates from many-cores promoting highly dynamic usage scenarios as already observable in today's "smart devices", where multiple and varying numbers of applications are running at different points in time. As a consequence, providing mapping of applications to processor cores which is optimal and predictable with respect to performance, timing, energy consumption, safety, security, etc. may not be guaranteed by static design-time optimization alone. At the same time, pure run-time optimization may result in unpredictable and non-optimal system states. This workshop investigates this field of tension of run-time, design-time, and hybrid design methodologies for the mapping of applications on many-core systems, particularly addressing the aspect of multiple conflicting objectives that drive the design.
This field of research includes numerous intermeshed aspects:
- Languages, Models, and Compilers: How to specify, analyze, parallelize, and compile programs which support dynamic usage scenarios in many-cores?
- Formal methods, Test, and Verification: How to analyze and verify predictable execution of applications despite unforeseeable run-time events?
- Optimization Techniques: Which design-time and run-time techniques as well as combinations of them provide optimized and predictable application mapping for many-cores?
- Architecture: Which architectural concepts are required to support predictability, run-time management and (self-)optimization?
Program:
Keynote: "Towards A Holistic Design Space Exploration for Automotive E/E Architectures" by Dr. Felix Reimann, Audi Electronics Venture GmbH
|
Time |
Paper Title and Authors |
|
08:30 - 08:50 |
Welcome & Introduction of Participants |
|
08:50 - 9:45 |
Keynote: Towards a Holistic Design Space Exploration for Automotive E/E Architectures |
|
9:45 - 10:15 |
Towards Redundant Communication through Hybrid Application Mapping |
|
10:15 - 10:50 |
Coffee Break |
|
10:50 - 11:20 |
A Many-Core Solution for the Multi-Objective Challenge in the Field of Dynamic Cycle Accurate Verification |
|
11:20 - 11:50 |
A Time Predictable Heterogeneous Multicore Processor for Hard Real-time GALS Programs |
|
11:50 - 12:20 |
A Novel NoC-Architecture for Fault Tolerance and Power Saving |
|
12:30 |
Lunch |
Location:
MOMAC will be held in conjunction with the 29th International Conference on Architecture of Computing Systems (ARCS 2016), on April 5, 2016 in Nuremberg, Germany.
Comittee:
Organizers
Michael Glaß (FAU, Germany, contact)
Stefan Wildermann (FAU, Germany, contact)
Technical Program Committee
Lars Bauer (Karlsruhe Institute of Technology (KIT), Germany)
Deepak Gangadharan (University of Pennsylvania, U.S.A.)
Markus Happe (ETH Zurich, Switzerland)
Christian Haubelt (University of Rostock, Germany)
Martin Lukasiewycz (Robert Bosch GmbH, Germany)
Akash Kumar (Technische Universität Dresden, Germany)
Sanaz Mostaghim (Otto von Guericke University of Magdeburg, Germany)
Mathias Pacher (University of Hannover, Germany)
Gianluca Palermo (Politecnico Di Milano, Italy)
Felix Reimann (Audi Electronics Venture GmbH, Germany)
Muhammad Shafique (Karlsruhe Institute of Technology (KIT), Germany)
Lucian Vintan (Lucian Blaga University of Sibiu, Romania)
Sebastian Voss (fortiss GmbH, Germany)