DATE Friday Workshop on
System-level Design
Methods for Deep Learning on
Heterogeneous Architectures
DATE 2021 Virtual Workshop, February 5, 2021
co-located with Conference on Design, Automation and Test in Europe
SLOHA 2021


♦ List of confirmed keynote and invited speakers:

Luca Benini, ETH Zürich, Switzerland
Michaela Blott, Xilinx Research, Ireland
Sorin Grigorescu, Transilvania University of Brasov and Elektrobit Automotive, Romania
Augusto Vega, IBM T. J. Watson Research Center, USA

Overview and Scope

Machine learning, particularly deep learning (DL), is the most quickly growing domain of artificial intelligence. DL is being applied in more and more disciplines for recognition, identification, classification, and prediction tasks. A large part of the activities is focused on image, video and speech processing, but more general signal processing tasks also benefit from DL.

Prominent application areas and markets include human-machine interaction using vocal commands, biological signals processing on wearable devices for medical and fitness applications, visual environment understanding applications such as those used in robotics and advanced driver assistance systems, or predictive maintenance in industrial automation. These applications are often embedded into a broader technical context, imposing stringent constraints on power and size. Thus, many applications should be executed on highly customized heterogeneous low-power computing platforms at the edge.

While on the one hand, there exists a large zoo of DL models and tools that target standard hardware platforms, there are many challenges when targeting heterogeneous and edge devices on the other hand. Several software and hardware design choices have to be made when developing such systems. How to automate the search for and efficiently deploy or synthesize a neural network on multiple target platforms, such as different heterogeneous low-power computing platforms and edge devices? How should the neural network look like to achieve the best possible result on a given hardware platform with limited computing power and energy budget?

The workshop's primary goal is to address these research questions and facilitate the implementation of DL applications on heterogeneous low-power computing platforms and edge devices, including accelerators such as (embedded) GPUs, FPGAs, CGRAs, and TPUs.

Topics of the SLOHA Workshop include, but are not limited to:

  • System-level design methods (e.g., scheduling, mapping) for DL
  • Design space exploration and optimization (accuracy, performance, energy efficiency, robustness, security and other non-functional properties)
  • Modeling of hardware-agnostic neural networks
  • Deep compression, quantization and pruning techniques for edge devices
  • Heterogeneous computing platforms, edge devices, neuromorphic hardware for DL
  • Modeling of DL target platforms
  • Compilers, code generators, and synthesis tools for deployment
  • Signal processing applications, use cases, and best practices

The workshop will also present some of the methods, tools, architectures, and results achieved in the European Union's Horizon 2020 project ALOHA ( and the KISS project funded by the German Federal Ministry of Education and Research.

Paper submission

Perspective authors are invited to submit original contributions (up to six pages) or extended abstracts describing work-in-progress or position papers (extended abstracts should not exceed two pages). All papers should be submitted in PDF file format following the standard IEEE conference template ( Papers may or may not hide author names and affiliation for optional blind reviewing.
All submissions have to be sent via the conference management system EasyChair.


Accepted papers will be included in an ePrint proceedings volume with Open Access. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.

Presentation formats

The regular papers judged as most valuable will be allocated a slot for an oral presentation. Registered authors will be able to present their work during a virtual poster session; due to the virtual format of the workshop, authors will need to prepare short presentations.

Important dates

Submission deadline for regular papers:November 6, 2020
Notification of acceptance (regular):November 25, 2020

Submission deadline for ext. abstracts:December 18, 2020
Notification of acceptance (ext. abstracts):January 8, 2021




General Co-Chairs

Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Paolo Meloni, University of Cagliari, Italy
Matteo Spallanzani, ETH Zürich, Switzerland
Matthias Ziegler, Fraunhofer Institute for Integrated Circuits (IIS), Erlangen, Germany

Program Committee

Luca Benini, ETH Zürich, Switzerland
Paolo Burgio, University of Modena and Reggio Emilia, Italy
Thomas Chau, Samsung AI Centre, UK
Holger Fröning, Heidelberg University, Germany
Ignacio Sañudo Olmedo, University of Modena and Reggio Emilia, Italy
Gregor Schiele, University Duisburg-Essen, Germany
Aviral Shrivastava, Arizona State University, USA
Andy Pimentel, University of Amsterdam, The Netherlands
Muhammad Shafique, New York University Abu Dhabi, United Arab Emirates
Todor Stefanov, Leiden University, The Netherlands
Jürgen Teich, Friedrich-Alexander University Erlangen-Nürnberg, Germany


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