SLOHA 2021
DATE Friday Workshop on


System-level Design
Methods for Deep Learning on
Heterogeneous Architectures


DATE 2021 Virtual Workshop, February 5, 2021
co-located with Conference on Design, Automation and Test in Europe

News

♦ Proceedings and final program are online
♦ Participation requires a valid DATE workshop registration. Please access the registration page at
     https://www.date-conference.com/registration
♦ Selected program highlights (keynote and invited speakers):

“In-Sensor ML — Heterogeneous Computing in a mW”
Luca Benini, ETH Zürich, Switzerland

“Specialization in Hardware Architectures for Deep Learning”
Michaela Blott, Xilinx Research, Ireland

“Vision Dynamics: A Learning Approach Towards Visually Controlled Autonomous Robotic Systems”
Sorin Grigorescu, Transilvania University of Brasov and Elektrobit Automotive, Romania

“SoCs for Autonomous Vehicles: Agile Design and Programmability Challenges”
Augusto Vega, IBM T. J. Watson Research Center, USA

Overview and Scope

Machine learning, particularly deep learning (DL), is the most quickly growing domain of artificial intelligence. DL is being applied in more and more disciplines for recognition, identification, classification, and prediction tasks. A large part of the activities is focused on image, video and speech processing, but more general signal processing tasks also benefit from DL.

Prominent application areas and markets include human-machine interaction using vocal commands, biological signals processing on wearable devices for medical and fitness applications, visual environment understanding applications such as those used in robotics and advanced driver assistance systems, or predictive maintenance in industrial automation. These applications are often embedded into a broader technical context, imposing stringent constraints on power and size. Thus, many applications should be executed on highly customized heterogeneous low-power computing platforms at the edge.

While on the one hand, there exists a large zoo of DL models and tools that target standard hardware platforms, there are many challenges when targeting heterogeneous and edge devices on the other hand. Several software and hardware design choices have to be made when developing such systems. How to automate the search for and efficiently deploy or synthesize a neural network on multiple target platforms, such as different heterogeneous low-power computing platforms and edge devices? How should the neural network look like to achieve the best possible result on a given hardware platform with limited computing power and energy budget?

The workshop's primary goal is to address these research questions and facilitate the implementation of DL applications on heterogeneous low-power computing platforms and edge devices, including accelerators such as (embedded) GPUs, FPGAs, CGRAs, and TPUs.

Topics of the SLOHA Workshop include, but are not limited to:

  • System-level design methods (e.g., scheduling, mapping) for DL
  • Design space exploration and optimization (accuracy, performance, energy efficiency, robustness, security and other non-functional properties)
  • Modeling of hardware-agnostic neural networks
  • Deep compression, quantization and pruning techniques for edge devices
  • Heterogeneous computing platforms, edge devices, neuromorphic hardware for DL
  • Modeling of DL target platforms
  • Compilers, code generators, and synthesis tools for deployment
  • Signal processing applications, use cases, and best practices

The workshop will also present some of the methods, tools, architectures, and results achieved in the European Union's Horizon 2020 project ALOHA (https://www.aloha-h2020.eu) and the KISS project (https://www.iis.fraunhofer.de/kiss) funded by the German Federal Ministry of Education and Research.

Proceedings

Access ePrint Proceedings here: https://arxiv.org/html/2102.00818

Paper submission

Perspective authors are invited to submit original contributions (up to six pages) or extended abstracts describing work-in-progress or position papers (extended abstracts should not exceed two pages). All papers should be submitted in PDF file format following the standard IEEE conference template (http://www.ieee.org/conferences_events/conferences/publishing/templates.html). Papers may or may not hide author names and affiliation for optional blind reviewing.
All submissions have to be sent via the conference management system EasyChair.

Publications

Accepted papers will be included in an ePrint proceedings volume with Open Access. Every accepted paper must have at least one author registered to the workshop by the time the camera-ready paper is due.

Presentation formats

The regular papers judged as most valuable will be allocated a slot for an oral presentation. Registered authors will be able to present their work during a virtual poster session; due to the virtual format of the workshop, authors will need to prepare short presentations.

Important dates

Submission deadline for regular papers:November 6, 2020 extended to November 16, 2020 AoE
Notification of acceptance (regular):December 17, 2020

Submission deadline for ext. abstracts:January 10, 2021 AoE
Notification of acceptance (ext. abstracts):January 15, 2021

Program and Proceedings

Friday, February 5, 2021
15:00 – 15:10
Welcome and Introduction
Frank Hannig
15:10 – 15:50
Keynote Speech 1
15:50 – 16:30
Session 1: Deep Learning at the Edge
Chair: Matthias Ziegler
15:50 – 16:00
Enabling Energy Efficient Machine Learning on a Ultra-Low-Power Vision Sensor for IoT
Francesco Paissan, Massimo Gottardi, and Elisabetta Farella
16:00 – 16:10
Bit Error Tolerance Metrics for Binarized Neural Networks
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Katharina Morik, Rodion Novkin, Lukas Pfahler, and Mikail Yayla
16:10 – 16:13
Fast Exploration of Weight Sharing Opportunities for CNN Compression
Etienne Dupuis, David Novo, Ian O'Connor, and Alberto Bosio
16:13 – 16:16
16:16 – 16:19
QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning
Dainius Jenkus, Fei Xia, Rishad Shafik, and Alex Yakovlev
16:30 – 16:40
Break
16:40 – 17:30
Session 2: Autonomous Vehicles
Chair: Paolo Meloni
17:30 – 17:35
Short Break
17:35 – 18:15
Session 3: Deep Learning Applications on Programmable Hardware
Chair: Matteo Spallanzani
17:35 – 17:45
Design and Deployment of Deep Learning Applications on Edge Computing Platforms: The ALOHA Framework
Paolo Meloni
17:48 – 17:51
Transparent FPGA Acceleration with TensorFlow
Simon Pfenning, Philipp Holzinger, and Marc Reichenbach
17:51 – 17:54
Hardware-efficient Residual Networks for FPGAs
Olivia Weng, Alireza Khodamoradi, and Ryan Kastner
17:54 – 18:04
Benchmarking Quantized Neural Networks on FPGAs with FINN
Quentin Ducasse, Pascal Cotret, Loïc Lagadec, and Robert Stewart
18:04 – 18:14
Why is FPGA-GPU Heterogeneity the Best Option for Embedded Deep Neural Networks?
Walther Carballo-Hernández, Maxime Pelcat, and François Berry
18:15 – 18:55
Keynote Speech 2
19:00
Closing

Keynote speakers:

Luca Benini, ETH Zürich, Switzerland
“In-Sensor ML — Heterogeneous Computing in a mW”

Abstract:
Luca Benini Edge Artificial Intelligence is the new megatrend, as privacy concerns and networks bandwidth/latency bottlenecks prevent cloud offloading of sensor analytics functions in many application domains, from autonomous driving to advanced prosthetic. The next wave of "Extreme Edge AI" pushes signal processing and machine learning aggressively into sensors and actuators, opening major research and business development opportunities. In this talk, I will focus on recent efforts in developing an AI-centric Extreme Edge heterogeneous computing platform  based on open source, parallel ultra-low power (PULP) customized ISA-RISC-V processors coupled with domain-specific accelerators, and I will look ahead to the next step: namely three-dimensional integration of sensors, mixed-signal front-ends and AI-processing engines.

Speaker's bio:
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. He served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award,the 2019 IEEE TCAD Donald O. Pederson Best Paper Award and the ACM/IEEE A. Richard Newton Award 2020.

 
Michaela Blott, Xilinx Research, Ireland
“Specialization in Hardware Architectures for Deep Learning”

Abstract:
Michaela Blott Neural Networks are playing a key role in enabling machine vision and speech recognition; however, their computational complexity and memory demands are challenging, which limits their deployment in particular within energy-constrained, embedded environments. To address these challenges, a broad spectrum of increasingly customized and heterogeneous hardware architectures has emerged.
During this talk, we will discuss various forms of specializations that have been leveraged by the industry with their impact on potential applications, flexibility, performance and efficiency. Furthermore, we will discuss how the specialization in hardware architectures can be automated through end-to-end tool flows.


Speaker's bio:
Michaela Blott is a Distinguished Engineer at Xilinx Research in Dublin, Ireland, where she heads a team of international scientists driving exciting research to define new application domains for Xilinx devices, such as machine learning, in both embedded and hyperscale deployments. She brings over 25 years of leading-edge computer architecture and advanced FPGA and board design, in research institutions (ETH Zürich and Bell Labs) and development organizations. She is heavily involved with the international research community serving as technical program chair, organizer, and technical program committee member for numerous conferences (FPL, ISFPGA, DATE, etc.). Over the years, she received several awards, most recently the Women in Tech Award 2019.

 

Invited speakers:

Sorin Grigorescu, Transilvania University of Brasov and Elektrobit Automotive, Romania
“Vision Dynamics: A Learning Approach Towards Visually Controlled Autonomous Robotic Systems”

Abstract:
Sorin Grigorescu Self-driving cars and autonomous vehicles are revolutionizing the automotive sector, shaping the future of mobility altogether. This talk introduces our work on learning-based Vision Dynamics for controlling autonomous vehicles, with a focus on the perception-planning-action control pipeline. The vision dynamics model is designed to estimate the dynamics of the environment and the controlled system's desired state trajectory, used as input to a constrained predictive controller. We propose to encode the vision model within different deep learning architectures, which act as nonlinear approximators for the high order state-space of the operating conditions. Additional to the Vision Dynamics theoretical framework, the talk also covers our AI Inference Engines approach for the design and development of autonomous driving applications. A data-driven V-Model is used in the development cycle, where prototyping takes place in the cloud according to the Software-in-the-Loop (SiL) paradigm, while deployment and evaluation on the target ECUs (Electronic Control Units) is performed as Hardware-in-the-Loop (HiL) testing.

Speaker's bio:
Prof. Dr. Sorin Grigorescu received the Ph.D. degree in Robotics from the University of Bremen, Germany, in 2010 and the Dipl.-Eng. Degree in Control Engineering and Computer Science from Transilvania University of Brasov, Romania, in 2006. Between 2006 and 2010 he was a member of the Institute of Automation, University of Bremen, where he coordinated the FRIEND service robotics project. Sorin is a professor at the Department of Automation, Transilvania University of Brasov, where he holds the Robotics Chair and leads the Robotics, Vision and Control Laboratory (ROVIS), which he founded in 2010. Since 2013, he is also affiliated with Elektrobit Automotive, where he is the global Head of Artificial Intelligence.

 
Augusto Vega, IBM T. J. Watson Research Center, USA
“SoCs for Autonomous Vehicles: Agile Design and Programmability Challenges”

Abstract:
Augusto Vega The phenomenon of self-driving (autonomous) vehicles is a symbol of the grand re-emergence of artificial intelligence and robotics as a promising technology. The most general model of future vehicular transportation is that of artificially intelligent, connected, autonomous vehicles. In defense applications, the scope would include military vehicle convoys on the ground, drone swarms in the air, as well as swarms of miniature robot submarines. In the commercial sector, the dominant market potential at this point is that of wirelessly connected, cloud-backed autonomous and semi-autonomous land vehicles.
In this talk, we are concerned about the task of designing efficient and resilient (secure) embedded SoCs in support of the above-mentioned vehicular swarm problem space. Such an SoC would be composed of a mix of different processing elements (PEs): e.g., general-purpose cores and various types of special-purpose accelerators. Such a heterogeneous, multi-core architecture is well-established in the art as an energy-efficient execution paradigm. However, such hardware-level heterogeneity generally presents itself as a difficult programmability challenge from a user perspective. The Domain-Specific SoC (or DSSoC) program under (DARPA MTO Electronics Resurgence Initiative (ERI)), is concerned with the problem of designing easily programmable, yet efficient SoCs (for an identified application domain) at low development cost. The IBM-led project under DSSoC is called EPOCHS: Efficient Programmability of Cognitive Heterogeneous Systems, where our chosen application domain is that represented by intelligent, connected autonomous vehicles. We present the novel elements of the EPOCHS approach to agile SoC design, where the strategy is to meet the programmability and efficiency metrics with the help of smart system software, supported where needed, by customized hooks in hardware.


Speaker's bio:
Augusto Vega is a Research Staff Member at IBM T. J. Watson Research Center (NY, USA) involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He is a promoter of the Adaptive Swarm Intelligence paradigm with potential application in autonomous/connected vehicles, drones, wearable devices, mobile health monitoring and cyber-physical systems. He has several pending/issued patents and published papers and has served on conference technical program committees in the area of highly-reliable power-efficient systems. Dr. Vega holds Ph.D. and M.Sc. degrees from Polytechnic University of Catalonia (UPC, Spain), and a B.Eng. degree from University of Buenos Aires (UBA, Argentina).

 

Organization

General Co-Chairs

Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Paolo Meloni, University of Cagliari, Italy
Matteo Spallanzani, ETH Zürich, Switzerland
Matthias Ziegler, Fraunhofer Institute for Integrated Circuits (IIS), Erlangen, Germany

Program Committee

Luca Benini, ETH Zürich, Switzerland
Paolo Burgio, University of Modena and Reggio Emilia, Italy
Thomas Chau, Samsung AI Centre, UK
Holger Fröning, Heidelberg University, Germany
Ignacio Sañudo Olmedo, University of Modena and Reggio Emilia, Italy
Gregor Schiele, University Duisburg-Essen, Germany
Aviral Shrivastava, Arizona State University, USA
Andy Pimentel, University of Amsterdam, The Netherlands
Muhammad Shafique, New York University Abu Dhabi, United Arab Emirates
Todor Stefanov, Leiden University, The Netherlands
Jürgen Teich, Friedrich-Alexander University Erlangen-Nürnberg, Germany

Contact

sloha2021@easychair.org

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